1. Field of the Invention
The present invention generally relates to semiconductor memory circuits and, more particularly, to a semiconductor memory circuit having high performance and low power characteristics.
2. Description of the Related Art
Conventional semiconductor memory circuits, such as ROM (read-only memory) circuits often make a trade-off between two separate architectures; one architecture for high performance characteristics, and the other architecture specific to low power consumption characteristics.
However, conventional devices and methods do not provide both architectures (high performance and low power) that are seamlessly interchangeable within a chip design. For example, in order to reduce the power consumption of a given chip design, a low-power ROM array may be substituted in place of a faster, high-power ROM array (represented as a second macro). In conventional structures, whenever such an architecture change is needed for a macro, the footprint between the two different macros (high power/low power) is often different. The xe2x80x9cfootprintxe2x80x9d is the surface area size of the macro within the circuit.
Even if the footprint is the same, the different macros will have very different timing characteristics. While the higher-power ROM array macro is designed to operate at a higher speed than the lower-power ROM array, there are additional timing differences between the two macros that are referred to as timing characteristics. Timing characteristics are different than the processing speed of the macro. Such timing characteristics relate to the type and number of inputs and outputs, as well as how the inputs and outputs sequence during any particular function. Even if the footprint and timing characteristics are the same, the different macros will have different devices and wiring internal to the macro.
Thus, there remains a need for a new and improved ROM device and method that provides high-power and low-power macros that are seamlessly interchangeable in a chip design. The invention described below provides such a method/structure.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional ROM devices, the present invention has been devised, and it is an object of the present invention to provide a structure and method for a ROM designed for selection between a memory device having high speed or a memory device requiring low operating power.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention, a method of designing an integrated circuit chip. The method includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, surface area size, external wiring pattern, and timing characteristics.
The method also includes designing a floorplan for the circuit, calculating the signal timing of the circuit, designing wires to connect elements of the circuit together, and recalculating the signal timing. After the macros are substituted, the method only repeats the recalculating of the signal timing. Also, the substituting of the second macro for the first macro is performed only if the performance characteristics indicate that the substituting would improve the performance characteristics. Such performance characteristics include operating speed, power consumption, etc.
The invention also includes a system for designing integrated circuits that has a first macro having a first power consumption rate and a second macro having a second power consumption rate different than the first power consumption rate. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics, and are designed to be seamlessly substituted for one another. The first macro and the second macro comprise a single design having different internal wiring connections between elements within the single design. The different wiring connections change an operating speed and a power consumption of the first macro when compared with the second macro.